1. Field of the Invention
The present invention relates in general to the field of packaging integrated circuits, and more specifically, to detecting solder interconnect fractures as they occur during the lifecycle of monitored components.
2. Description of the Related Art
Integrated circuit technology continues to evolve, resulting in chips with increased clock speeds, higher power consumption, and larger numbers of inputs and outputs. Corresponding advances in integrated circuit fabrication technology have resulted in higher levels of integration, increased density, and growth in die sizes, any or all of which can pose additional challenges when packaging and mounting semiconductor devices.
A semiconductor device is an integrated circuit in packaged form, usually mounted to a printed wire board (PWB) or other type of carrier, operating as a processing unit, memory, controller or any other electronic device. Semiconductor package and packaging techniques are designed to protect the integrated circuit from mechanical and environmental damage, assist thermal dissipation during operation, and most relevant to the present invention, provide electrical connection between the integrated circuit and external electrical devices.
A fundamental problem in semiconductor package mounting is brittle solder joint fractures. Unlike fatigue failures, these fractures typically occur during a monotonic (non-reversing) stress event such as drop or high strain rate flexure. Monotonic stress events can occur during board assembly/test, shipment/handling operations, and/or actual end-use. For example, in-circuit test (ICT) and certain assembly operations, such as manual connector insertion and printed wire board (PWB) edge-guide snap-off, are often associated with high strain and strain-rate. Such operations can also result in high PWB flexural loading, depending upon system configuration, assembly location, and other factors. Because the method and apparatus of the present invention can be used with a wide variety of solder-based electrical connections and associated geometries, the terms “solder joint” and “solder interconnect” will be used interchangeably.
Although they occur infrequently, brittle solder interconnect fractures are nonetheless a major concern given the possibility of undetected failures. Some brittle solder joint fractures may be detected prior to shipment, while others may go undetected due to either incomplete fracture of the solder joint, or ohmic contact between fractured surfaces during electrical monitoring. The presence of undetected, yet damaged, solder joints compromises the potential functionality and reliability of the electronic device during end-use operation.
While brittle fractures have been documented for ball grid array (BGA) packages using electrolytic nickel/gold (Ni/Au)-plated and solder-over-copper (Cu) substrates, the majority of brittle fractures involve packages using electro-less nickel, immersion gold (ENIG) plated BGA substrates. Brittle fracture for BGA packages using ENIG plating occurs between the phosphorous (P) rich Ni surface and the nickel-tin/tin-copper/nickel (NiSn/SnCu/Ni) intermetallic layer. Approaches for the prevention of BGA brittle fracture can include improvement in solder joint fracture resistance, as well as reduction of applied strain.
Solder joint fracture resistance can also be dependent upon the characteristics of the solder used in assembly. For example, the strength characteristics of SnPb (tin-lead) and Pb-free solder alloys are highly strain-rate dependent, but Pb-free solder alloys, such as tin-gold-copper (SnAgCu), may prove more sensitive to brittle fracture than eutectic SnPb solder. Although solder strength typically improves with increased strain-rate, the higher plastic modulus at elevated strain levels can result in increased interfacial strain at the pad/solder region under flexural or impact loading conditions.
Currently, various destructive tests including drop, shock, vibration, twist, and high-speed monotonic bend, are used to correlate fracture resistance to force, deflection, and/or acceleration. When applied at the component and board level, these tests can be useful for assessing the integrity of solder joints resulting from different combinations of components and/or assembly processes. Other destructive solder joint integrity test methods approximate actual conditions associated with solder joint brittle fracture and can yield more accurate assessments of brittle fracture resistance. For example, solder interconnect brittle fracture resistance during drop conditions can be characterized using drop testing of production and/or test circuit board assemblies. A destructive industry test method used to assess BGA solder joint integrity, solder ball shear/pull testing, does not consistently detect microstructural weaknesses at the pad/solder interfaces where brittle failures occur. Furthermore, solder ball shear and/or pull testing is not applicable to BGA components assembled on a PWB.
While these destructive test methods provide useful tools for component manufacturers to optimize the brittle fracture resistance of their product, they are impractical for in-line solder joint integrity monitoring and/or end-use, either of which require a non-destructive testing approach. Furthermore, the results of these destructive tests are only applicable to the specific component and board configuration under test.
What is needed is a non-destructive solder joint integrity monitoring system that can detect existing damage, identify new or incipient fractures, and is capable of being implemented across multiple component configurations.